1. Field of Invention
This invention relates to a controller integrated within a computer memory which is used for memory testing during wafer testing and for performing additional useful functions when installed in a User's system. For the purposes of this application the terms Controller and Processor will mean the same thing and the Test CPU (TCPU) is a Processor. The term User includes the end user of the memory such as when the memory is installed in a Personal Computer or other device.
2. Background of the Invention
Typically, in addition to hard errors such as stuck nodes, memories are subject to errors caused by a sensitivity to the pattern of data stored in the memory. It is not feasible to test every combination of data bits in a large memory because it would simply take too long. Therefore, patterns are selected that are either predicted or known to cause errors. Pattern sensitivities can change as processes are changed; thus it may be necessary to change the test suite as wafers are processed. It is also possible that new pattern sensitivities may be discovered after a part is installed in a User's system. When this new pattern is added to the test suite the yield goes down. To bring the yield back up the process is tweaked and/or the part is redesigned.
In the manufacturing process, after a wafer is fabricated the common practice is to test each IC by positioning a test head containing probes over each IC one at a time to contact the IC's pads, exercise the IC to determine whether it is good, and mark the bad ones. After all the ICs on the wafer are tested they are cut from the wafer and the good ones are packaged. These are then tested again. By testing the ICs before they are cut from the wafer the bad ones can be discarded before they are packaged, thus saving money. However, as ICs become more complex, the time needed to test them increases. This is especially true with memories because of the need to test for memory sensitivity to data patterns. ICs are also commonly tested at different speeds because memories that fail at the highest rated speed may perform properly at lower speeds. Good memories are then sorted by speed so the lower speed devices can be sold instead of thrown away. Another problem faced by memory manufacturers is that as ICs become faster it becomes more difficult to test them at their rated speed due to the limitations imposed by using a test head.
Another common practice (called burn-in) is to subject the wafer to elevated temperatures. Premature IC failure tends to occur early in an IC's expected operating life. Subjecting the wafer to elevated temperatures accelerates the early-failure rate of the ICs.
Burn-in is more effective if the ICs on the wafer are powered during the test. One method to accomplish this is taught in U.S. Pat. No. 5,461,328 Fixture for burn-in testing of semiconductor wafers issued Oct. 24, 1995, to Devereaux, et al. Another method is taught in U.S. Pat. No. 5,766,979 Wafer level contact sheet and method of assembly issued Jun. 16, 1998, to Budnaitis. A further method is taught in U.S. Pat. No. 6,020,750 Wafer test and burn-in platform using ceramic tile supports issued Feb. 1, 2000, to Berger, et al.
However, these methods only apply power to the ICs on the wafer. They do not allow the ICs to be tested during burn-in. Some ICs may work perfectly well at room temperature and after burn-in but fail to work properly at the elevated temperature experienced during burn-in. Other ICs may work at room temperature, after burn-in, and at the elevated temperature, but fail to work at temperatures between room temperature and the elevated temperature. Since ICs are also rated to operate at a minimum temperature the same problem exists when testing these ICs at this low temperature. Some ICs may work at room temperature and low temperature but fail to work properly at intermediate temperatures.
Therefore a need exists to be able to continuously test ICs at the wafer level during testing, whether at elevated temperatures, low temperatures, or temperatures in-between, and keep a record of the results so that only good devices are packaged and sold to customers.
U.S. Pat. No. 4,757,503 Self-testing dynamic ram issued Jul. 12, 1988 to Hayes, et al. contains a built-in testing circuit using hard-wired logic. Changing the test suite requires redesigning the IC.
U.S. Pat. No. 6,154,861 Method and apparatus for built-in self-test of smart memories issued Nov. 28, 2000, to Harward contains a Test Controller (FIG. 4), the details of which are not disclosed. There is no suggestion that the Test Controller can be reprogrammed after the IC is fabricated. Likewise, there is no suggestion that the Test Controller can be used for other than memory testing.
Accordingly, one of the objects and advantages of the present invention is to provide a programmable processor integrated into the memory for efficiently testing memories during both wafer testing and after packaging. An additional object and advantage is to provide a programmable processor integrated into the memory that can be used for functions such as graphics primitives and data matching. Further objects and advantages of my invention will become apparent from a consideration of the drawings and ensuing description.